Google TPU 8tx and 8i Max Join the Eighth-Gen Lineup

Google has expanded its eighth generation of Tensor Processing Units with two new systems, TPU 8tx for secure, confidential inference and TPU 8i Max for massive context windows. The announcement, written by Amin Vahdat, Google’s SVP and Chief Technologist for AI and Infrastructure, says this is the first time the company has introduced four TPU systems in a single year. They join the training-focused TPU 8t and the inference-focused TPU 8i that Google unveiled at Cloud Next in April, which it credits with up to 2.7 times better training performance and 80% better inference price performance than the previous generation.

Vahdat draws a line between a new chip and a new system. A chip takes years of design and manufacturing; a system is how Google packages the compute, memory, networking and security around that chip, and it can be rebuilt in months. Both new products are systems in that sense. TPU 8tx uses the same silicon as TPU 8t, pairs it with 5th Generation AMD EPYC CPU hosts, and builds security into the hardware so that sensitive data and model weights stay protected and isolated even while they are in use, rather than being decrypted in memory. It also borrows the low-latency Boardfly network from TPU 8i, which Google says gives up to 2x lower latency than TPU 8t with a near-zero performance penalty.

Google is aiming TPU 8tx at regulated enterprises and governments that run frontier or proprietary models and agents next to their most sensitive data. Because it pairs training-grade compute with an inference network, teams can fine-tune on private data, distil large models into smaller ones and train agents with reinforcement learning on the same system, without moving data between separate clusters. TPU 8i Max tackles a different bottleneck, the memory wall: it combines two TPU 8i chips on one package for double the compute, double the SRAM and double the HBM bandwidth of TPU 8i, and fits twice the silicon into the existing rack footprint. The target is many agents working across a whole codebase or hours of video at once.

Much of the post is about software, and about making TPUs feel less exotic. Google open-sourced TorchTPU in October, so PyTorch code and Hugging Face models run natively, alongside TPU backends for the vLLM and SGLang inference engines. A new open-source TPU agent suite, in preview, plugs into Claude Code, Cursor and Google Antigravity to automate onboarding, diagnose bottlenecks and autotune kernels in plain language. An Agent Compute Engine suspends idle agent sessions and moves their working memory off the chip in milliseconds, and the newly open-sourced TPU Sync treats HBM, host DRAM, shared storage and the network as one memory hierarchy, which Google says cuts KV transfer latency and time to first token by more than 90%. Cloud Pathways and GKE dynamic slicing are now generally available; Google says the latter speeds up job startup by up to 5x and fault recovery by up to 4.5x.

The commercial backdrop is the most telling line in the post. TPUs, Vahdat writes, are now a rapidly growing business with nearly 100 customers, from frontier labs to trading firms, retailers and universities, and some customers now install TPUs in their own data centres. The post gives no pricing or availability dates for either system; Google pointed to a livestreamed broadcast and its Cloud site for details. What it does show is a chip business being run like a product line, with variants cut for specific buyers rather than one accelerator per generation, which is a direct answer to the way Nvidia sells its systems.